module counter(clk,rst,en,sec_ge,sec_shi,cout);
    input clk;
    input rst;
    input en;
    output [3:0] sec_ge,sec_shi;
    output cout;
    reg [5:0] counter=0;
    reg cout=0;
    assign sec_ge=counter%10;
    assign sec_shi=counter/10;
    always@(posedge clk or negedge rst)
        begin
            if (!rst)
                counter<=0;
            else if(en)
                begin
                    if(counter<59)
                        counter<=counter+1;
                    else
                        counter<=0;
                end
        end
    always@(counter)
        begin
            if(counter==59)
                cout<=1;
            else
                cout<=0;
        end
endmodule
